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rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. AD7476A/ad7477a/ad7478a 2.35 v to 5.25 v, 1 msps, 12-/10-/8-bit adcs in 6-lead sc70 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 features fast throughput rate: 1 msps specified for v dd of 2.35 v to 5.25 v low power: 3.6 mw typ at 1 msps with 3 v supplies 12.5 mw typ at 1 msps with 5 v supplies wide input bandwidth: 71 db snr at 100 khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface spi/qspi/microwire/dsp compatible standby mode: 1 a max 6-lead sc70 package 8-lead soic package applications battery-powered systems personal digital assistants medical instruments mobile communications instrumentation and control systems data acquisition systems high speed modems optical sensors functional block diagram 8-/10-/12-bit successive- approximation adc control logic AD7476A/ad7477a/ad7478a gnd v dd v in sclk sdata cs t/h general description the AD7476A/ad7477a/ad7478a are 12-bit, 10-bit, and 8-bit, high speed, low power, successive-approximation adcs, respec- tively. t he parts operate from a single 2.35 v to 5.25 v power supply and feature throughput rates up to 1 msps. the parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 13 mhz. the conversion process and data acquisition are controlled using cs and the serial clock, allowing the devices to interface with microprocessors or dsps. the input signal is sampled on the falling edge of cs , and the conversion is also initiated at this point. there are no pipelined delays associated with the part. the AD7476A/ad7477a/ad7478a use advanced design tech- niques to achieve low power dissipation at high throughput rates. the reference for the part is taken internally from v dd. this allows the widest dynamic input range to the adc. thus, the analog input range for the part is 0 to v dd . the conversion rate is deter- mined by the sclk. product highlights 1. first 8-/10-/12-bit adcs in a sc70 package. 2. high throughput with low power consumption. 3. flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the conver- sion time to be reduced through the serial clock speed increase. this allows the average power consumption to be reduced when a power-down mode is used while not converting. the part also features a power-down mode to maximize power efficiency at lower throughput rates. current consumption is 1 a max and 50 na typically when in power-down mode. 4. reference derived from the power supply. 5. no pipeline delay. the parts feature a standard successive- approximation adc with accurate control of the sampling instant via a cs input and once-off conversion control. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation.
rev. 0 e2e AD7476A/ad7477a/ad7478a (v dd = 2.35 v to 5.25 v, f sclk = 20 mhz, f sample = 1 msps, unless otherwise noted; t a = t min to t max , unless otherwise noted.) AD7476Aespecifications 1 parameter a grade 1, 2 b grade 1, 2 unit test conditions/comments dynamic performance f in = 100 khz sine wave signal-to-noise + distortion (sinad) 3 70 70 db min v dd = 2.35 v to 3.6 v, t a = 25 c 69 69 db min v dd = 2.4 v to 3.6 v 71.5 71.5 db typ v dd = 2.35 v to 3.6 v 69 69 db min v dd = 4.75 v to 5.25 v, t a = 25 c 68 68 db min v dd = 4.75 v to 5.25 v signal-to-noise ratio (snr) 3 71 71 db min v dd = 2.35 v to 3.6 v, t a = 25 c 70 70 db min v dd = 2.4 v to 3.6 v 70 70 db min v dd = 4.75 v to 5.25 v, t a = 25 c 69 69 db min v dd = 4.75 v to 5.25 v total harmonic distortion (thd) 3 C C C C C C C C C C C
rev. 0 AD7476A/ad7477a/ad7478a e3e ad7477aespecifications 1 (v dd = 2.35 v to 5.25 v, f sclk = 20 mhz, f sample = 1 msps, unless otherwise noted; t a = t min to t max , unless otherwise noted.) parameter a grade 1, 2 b grade 1, 2 unit test conditions/comments power requirements v dd 2.35/5.25 2.35/5.25 v min/max i dd digital i/ps = 0 v or v dd normal mode (static) 2.5 2.5 ma typ v dd = 4.75 v to 5.25 v, sclk on or off 1.2 1.2 ma typ v dd = 2.35 v to 3.6 v, sclk on or off normal mode (operational) 3.5 3.5 ma max v dd = 4.75 v to 5.25 v, f sample = 1 msps 1.7 1.7 ma max v dd = 2.35 v to 3.6 v, f sample = 1 msps full power-down mode (static) 1 1 a max typically 50 na full power-down mode (dynamic) 0.6 0.6 ma typ v dd = 5 v, f sample = 100 ksps 0.3 0.3 ma typ v dd = 3 v, f sample = 100 ksps power dissipation 7 normal mode (operational) 17.5 17.5 mw max v dd = 5 v, f sample = 1 msps 5.1 5.1 mw max v dd = 3 v, f sample = 1 msps full power-down mode 5 5 w max v dd = 5 v 33 w max v dd = 3 v notes 1 temperature range from C C C C C
rev. 0 e4e AD7476A/ad7477a/ad7478a ad7478aespecifications 1 ( v dd = 2.35 v to 5.25 v, f sclk = 20 mhz, f sample = 1 msps, unless otherwise noted; t a = t min to t max , unless otherwise noted.) parameter a grade 1, 2 unit test conditions/comments logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max v dd = 5 v 0.4 v max v dd = 3 v input current, i in , sclk pin 0.5 a max typically 10 na, v in = 0 v or v dd input current, i in , cs pin 10 na typ input capacitance, c in 5 5 pf max logic outputs output high voltage, v oh v dd C C C C C C
rev. 0 AD7476A/ad7477a/ad7478a e5e parameter a grade 1, 2 unit test conditions/comments dc accuracy resolution 8 bits integral nonlinearity 3 0.3 lsb max differential nonlinearity 3 0.3 lsb max guaranteed no missed codes to 8 bits offset error 3, 4 0.3 lsb max gain error 3, 4 0.3 lsb max total unadjusted error (tue) 3, 4 0.5 lsb max analog input input voltage ranges 0 to v dd v dc leakage current 0.5 a max input capacitance 20 pf typ track-and-hold in track, 6 pf typ when in hold logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max v dd = 5 v 0.4 v max v dd = 3 v input current, i in , sclk pin 0.5 a max typically 10 na, v in = 0 v or v dd input current, i in , cs pin 10 na typ input capacitance, c in 5 5 pf max logic outputs output high voltage, v oh v dd C C
rev. 0 e6e AD7476A/ad7477a/ad7478a timing specifications 1 (v dd = 2.35 v to 5.25 v; t a = t min to t max , unless otherwise noted.) limit at t min , t max parameter AD7476A/ad7477a/ad7478a unit description f sclk 2 20 khz min 3 20 mhz max t convert 16 t sclk AD7476A 14 t sclk ad7477a 12 t sclk ad7478a t quiet 50 ns min minimum quiet time required between bus relinquish and start of next conversion t 1 10 ns min minimum cs pulsewidth t 2 10 ns min cs to sclk setup time t 3 4 22 ns max delay from cs until sdata three-state disabled t 4 4 40 ns max data access time after sclk falling edge t 5 0.4 t sclk ns min sclk low pulsewidth t 6 0.4 t sclk ns min sclk high pulsewidth t 7 5 sclk to data valid hold time 10 ns min v dd 3.3 v 9.5 ns min 3.3 v < v dd 3.6 v 7 ns min v dd > 3.6 v t 8 6 36 ns max sclk falling edge to sdata high impedance see note 7 ns min sclk falling edge to sdata high impedance t power-up 8 1 s max power-up time from full power-down notes 1 sample tested at 25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. 2 mark/space ratio for the sclk input is 40/60 to 60/40. 3 minimum f sclk at which specifications are guaranteed. 4 measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.8 v or 1.8 v when v dd = 2.35 v and 0.8 v or 2.0 v for v dd > 2.35 v. 5 measured with 30 pf load capacitor. 6 t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the meas ured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 8 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 t 7 values also apply to t 8 minimum values. 8 see power-up time section. specifications subject to change without notice. timing example 1 having f sclk = 20 mhz and a throughput of 1 msps gives a cycle time of t 2 + 12.5 (1/f sclk ) + t acq = 1 s. with t 2 = 10 ns min, this leaves t acq to be 365 ns. this 365 ns satisfies the requirement of 250 ns for t acq . from figure 3, t acq is comprised of 2.5 (1/f sclk ) + t 8 + t quiet , where t 8 = 36 ns max. this allows a value of 204 ns for t quiet , satisfying the minimum requirement of 50 ns. cs sclk sdata t 2 t 6 t 3 t 4 t 7 t 5 t 8 t convert t q uiet zero zero zero db11 db10 db2 db1 db0 b three-state three- state z 4 leading zeros 12 345 13 14 15 16 t 1 figure 2. AD7476A serial interface timing diagram to output pin c l 50pf 200 a i oh 200 a i ol 1.6v figure 1. load circuit for digital output timing specifications
rev. 0 AD7476A/ad7477a/ad7478a e7e absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . C C C C C C ja thermal impedance . . . . . . . . . . . . . . . . . . 205.9 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . 43.74 c/w cs sclk t 2 t convert b 1 2345 13141516 c t 8 t q uiet t acq 12.5(1/f sclk ) 1/throughput figure 3. serial interface timing example timing example 2 having f sclk = 5 mhz and a throughput of 315 ksps gives a cycle time of t 2 + 12.5 (1/f sclk ) + t acq = 3.174 s. with t 2 = 10 ns min, this leaves t acq to be 664 ns. this 664 ns satisfies the requirement of 250 ns for t acq . from figure 3, t acq is comprised of 2.5 (1/f sclk ) + t 8 + t quiet , t 8 = 36 ns max. this allows a value of 128 ns for t quiet , satisfying the minimum requirement of 50 ns. as in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still neces sary to leave 50 ns minimum t quiet between conversions. in example 2, the signal should be fully acquired at approximately point c in figure 3. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment, and can discharge without detection. although the AD7476A/ad7477a/ad7478a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device sc70 package ja thermal impedance . . . . . . . . . . . . . . . . . . 340.2 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . 228.9 c/w lead temperature, soldering vapor phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kv notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. ordering guide temperature linearity package model range error (lsb) 1 option 2 branding AD7476Aaks C C C C C C C
rev. 0 e8e AD7476A/ad7477a/ad7478a pin configurations pin function description mnemonic function cs chip select. active low logic input. this input provides the dual function of initiating conversions on the AD7476A/ad7477a/ad7478a and also frames the serial data transfer. v dd power supply input. the v dd range for the AD7476A/ad7477a/ad7478a is from 2.35 v to 5.25 v. gnd analog ground. ground reference point for all circuitry on the AD7476A/ad7477a/ad7478a. all analog input signals should be referred to this gnd voltage. v in analog input. single-ended analog input channel. the input range is 0 to v dd . sdata data out. logic output. the conversion result from the AD7476A/ad7477a/ad7478a is provided on this output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream from the AD7476A consists of four leading zeros followed by the 12 bits of conversion data that is provided msb first. the data stream from the ad7477a consists of four leading zeros followed by the 10 bits of conversion data followed by two trailing zeros, which is provided msb first. the data stream from the ad7478a consists of four leading zeros followed by the 8 bits of conversion data followed by four trailing zeros, which is provided msb first. sclk serial clock. logic input. sclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source for the AD7476A/ad7477a/ad7478a
rev. 0 AD7476A/ad7477a/ad7478a e9e terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. for the AD7476A/ ad7477a/ad7478a, the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., agnd + 1 lsb. gain error this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal, i.e., v ref C signal-to- ( noise + distortion ) = (6.02 n + 1.76) db thus, it is 74 db for a 12-bit converter, 62 db for a 10-bit con- verter, and 50 db for an 8-bit converter. total unadjusted error this is a comprehensive specification that includes the gain, linearity, and offset errors. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. it is defined as: thd db vvvv v () = ++++ 20 2 3 2 4 2 5 2 6 2 1 log v 2 where v 1 is the rms amplitude of the fundamental, and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum. but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb, where m and n= 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa C C C
rev. 0 e10e AD7476A/ad7477a/ad7478a frequency e khz 5 e55 e115 0 500 50 snr e db 100 150 200 250 300 350 400 450 e15 e35 e75 e95 8192 point fft v dd = 2.7v f sample = 1msps f in = 100khz sinad = 72.05db thd = e82.87db sfdr = e87.24db tpc 1. AD7476A dynamic performance at 1 msps frequency e khz e45 e105 snr e db e5 e25 e65 e85 8192 point fft v dd = 2.35v f sample = 1msps f in = 100khz sinad = 61.67db thd = e79.59db sfdr = e82.93db 0 500 50 100 150 200 250 300 350 400 450 tpc 2. ad7477a dynamic performance at 1 msps frequency e khz 5 e25 e55 snr e db e5 e15 e35 e45 8192 point fft v dd = 2.35v f sample = 1msps f in = 100khz sinad = 49.77db thd = e75.51db sfdr = e70.71db 0 500 50 100 150 200 250 300 350 400 450 e75 e65 e85 e95 tpc 3. ad7478a dynamic performance at 1 msps frequency e khz e66 e69 e72 10 1000 sinad e db 100 e67 e68 e70 e71 e73 e74 v dd = 5.25v v dd = 2.35v v dd = 2.7v v dd = 4.75v v dd = 3.6v tpc 4. AD7476A sinad vs. input frequency at 1 msps performance curves tpc 1, tpc 2, and tpc 3 show a typical fft plot for the AD7476A, ad7477a, and ad7478a, respectively at 1 msps sample rate and 100 khz input frequency. tpc 4 shows the signal-to-(noise + distortion) ratio performance versus input frequency for various supply voltages while sampling at 1 msps with an sclk frequency of 20 mhz for the AD7476A. tpc 5 and tpc 6 show inl and dnl performance for the AD7476A. tpc 7 shows a graph of the total harmonic distortion versus analog input frequency for different source impedances when using a supply voltage of 3.6 v and sampling at a rate of 1 msps (see analog input section). tpc 8 shows a graph of the total harmonic distortion versus analog input signal frequency for various supply voltages while sampling at 1 msps with a sclk frequency of 20 mhz. t ypical performance characteristics
rev. 0 AD7476A/ad7477a/ad7478a e11e code 1.0 0.4 e0.2 0 1024 inl error e lsb 512 0.8 0.6 0.2 0 e0.4 e0.6 e0.8 e1.0 1536 2048 2560 3072 3584 4096 v dd = 2.35v temp = 25 c f sample = 1msps tpc 5. AD7476A inl performance code 1.0 0.4 e0.2 0 1024 dnl error e lsb 512 0.8 0.6 0.2 0 e0.4 e0.6 e0.8 e1.0 1536 2048 2560 3072 3584 4096 v dd = 2.35v temp = 25 c f sample = 1msps tpc 6. AD7476A dnl performance input frequency e khz 0 e30 e60 10 1000 thd e db 100 e10 e20 e40 e50 e70 e80 e90 v dd = 3.6v r in = 10k r in = 1k r in = 130 r in = 13 r in = 0 tpc 7. thd vs. analog input frequency for various source impedance input frequency e khz e60 e75 e90 10 1000 thd e db 100 e65 e70 e80 e85 v dd = 5.25v v dd = 2.35v v dd = 2.7v v dd = 4.75v v dd = 3.6v tpc 8. thd vs. analog input frequency for various supply voltages
rev. 0 e12e AD7476A/ad7477a/ad7478a circuit information the AD7476A/ad7477a/ad7478a are fast, micropower, 12-/ 10-/8-bit, single-supply a/d converters, respectively. the parts can be operated from a 2.35 v to 5.25 v supply. when operated from either a 5 v supply or a 3 v supply, the AD7476A/ ad7477a/ad 7478a are capable of throughput rates of 1 msps when provided with a 20 mhz clock. the AD7476A/ad7477a/ad7478a provide the user with an on-chip track-and-hold, a/d converter and a serial interface housed in a tiny 6-lead sc70 package or 8-lead msop package, which offers the user considerable space-saving advantages over alternative solutions. the serial clock input accesses data from the part but also provides the clock source for the successive- approximation a/d converter. the analog input range is 0 to v dd . the adc does not require an external reference or a reference on-chip. the reference for the AD7476A/ad7477a/ ad7478a is derived from the power supply and thus gives the widest dynamic input range. the AD7476A/ad7477a/ad7478a also feature a power-down option to allow power saving between conversions. the power- down feature is implemented across the standard serial interface, as described in the modes of operation section. converter operation the AD7476A/ad7477a/ad7478a is a successive-approximation, analog-to-digital converter based around a charge redistribution dac. figures 4 and 5 show simplified schematics of the adc. figure 4 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on v in . charge redistribution dac control logic comparator sw2 sampling capacitor acq uisition phase sw1 a b a gnd v dd /2 v in figure 4. adc acquisition phase when the adc starts a conversion, see figure 5, sw2 will open and sw1 will move to position b, causing the comparator to become unbalanced. the control logic and the charge redistribution dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. figure 6 shows the adc transfer function. charge redistribution dac control logic comparator sw2 sampling capacitor conversion phase sw1 a b a gnd v dd /2 v in figure 5. adc conversion phase adc transfer function the output coding of the AD7476A/ad7477a/ad7478a is straight binary. the designed code transitions occur at the successive integer lsb values, i.e., 1 lsb, 2 lsbs, and so on. the lsb size is v dd /4096 for the AD7476A, v dd /1024 for the ad7477a, and v dd /256 for the ad7478a. the ideal transfer characteristic for the AD7476A/ad7477a/ad7478a is shown in figure 6. 000...000 0v adc code analog input 111...111 000...001 000...010 111...110 111...000 011...111 1lsb = v dd /256 (ad7478a) 1lsb +v dd e1lsb 1lsb = v dd /1024 (ad7477a) 1lsb = v dd /4096 (AD7476A) figure 6. AD7476A/ad7477a/ad7478a transfer characteristic
rev. 0 AD7476A/ad7477a/ad7478a e13e typical connection diagram figure 7 shows a typical connection diagram for the AD7476A/ ad7477a/ad7478a. v ref is taken internally from v dd and, as such, v dd should be well decoupled. this provides an analog input range of 0 v to v dd . the conversion result is output in a 16-bit word with four leading zeros followed by the msb of the 12-bit, 10-bit, or 8-bit result. the 10-bit result from the ad7477a will be followed by two trailing zeros and the 8-bit result from the ad7478a will be followed by four trailing zeros. alternatively, because the supply current required by the AD7476A/ ad7477a/ad7478a is so low, a precision reference can be used as the supply source to the AD7476A/ad7477a/ad7478a. a ref19x voltage reference (ref195 for 5 v or ref193 for 3 v) can be used to supply the required voltage to the adc (see figure 7). this configuration is especially useful if your power supply is quite noisy or if the system supply voltages are at some value other than 5 v or 3 v (e.g., 15 v). the ref19x will output a steady voltage to the AD7476A/ad7477a/ad7478a. if the low dropout ref193 is used, the current it needs to supply to the AD7476A/ad7477a/ad7478a is typically 1.2 ma. when the adc is converting at a rate of 1 msps, the ref193 will need to supply a maximum of 1.7 ma to the AD7476A/ ad7477a/ ad7478a. the load regulation of the ref193 is typi- cally 10 ppm/ma (v s = 5 v), which results in an error of 17 ppm (51 v) for the 1.7 ma drawn from it. this corresponds to a 0.069 lsb error for the AD7476A with v dd = 3 v from the ref193, a 0.017 lsb error for the ad7477a, and a 0.0043 lsb error for the ad7478a. for applications where power con sumption is of concern, the power-down mode of the adc and the sleep mode of the ref19x reference should be used to improve power performance. see modes of operation section. AD7476A/ ad7477a/ ad7478a sclk sdata cs v in gnd 0v to v dd input v dd c/ p serial interface 0.1 f 1 f t ant ref193 1.2ma 680nf 10 f 0.1 f 3v 5v supply figure 7. ref193 as power supply to AD7476A/ ad7477a/ad7478a table i provides some typical performance data with various references used as a v dd source for 100 khz input tone at room temperature under the same setup conditions. table i. AD7476A typical performance for various voltage references ic reference tied AD7476A snr performance to v dd (db) ad780 @ 3 v 72.65 ref193 72.35 ad780 @ 2.5 v 72.5 ref192 72.2 ref43 72.6 analog input figure 8 shows an equivalent circuit of the analog input structure of the AD7476A/ad7477a/ad7478a. the two diodes d1 and d2 provide esd protection for the analog input. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mv. this will cause these diodes to become forward biased and start conducting current into the sub- strate. 10 ma is the maximum current these diodes can conduct without causing irreversible damage to the part. the capacitor c1 in figure 8 is typically about 6 pf and can primarily be attributed to pin capacitance. the resistor r1 is a lumped component made up of the on resistance of a switch. this resistor is typically about 100 . the capacitor c2 is the adc sampling capacitor and has a capacitance of 20 pf typically. for ac applications, remov- ing high frequency components from the analog input signal is recommended by use of a band-pass filter on the relevant analog input pin. in applications where harmonic distortion and signal- to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances will significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the op amp will be a function of the particular application. d1 d2 r1 c2 20pf v dd v in c1 6pf conversion phase e switch open track phase e switch closed figure 8. equivalent analog input circuit
rev. 0 e14e AD7476A/ad7477a/ad7478a table ii provides some typical performance data with various op amps used as the input buffer for 100 khz input tone at room temperature under the same setup conditions. table ii. AD7476A typical performance with various input buffers, v dd = 3 v op amp in the AD7476A snr performance input buffer (db) ad711 72.3 ad797 72.5 ad845 71.4 when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance will depend on the amount of total harmonic distortion (thd) that can be tolerated. the thd will increase as the source impedance increases and the performance will degrade. see tpc 7. digital inputs the digital inputs applied to the AD7476A/ad7477a/ ad7478a are not limited by the maximum ratings that limit the analog input. instead, the digital inputs applied can go to 7 v and are not restricted by the v dd + 0.3 v limit as on the analog input. for example, if the AD7476A/ad7477a/ad7478a were operated with a v dd of 3 v, then 5 v logic levels could be used on the digital inputs. however, it is important to note that the data output on sdata will still have 3 v logic levels when v dd = 3 v. another advantage of sclk and cs not being restricted by the v dd + 0.3 v limit is the fact that power supply sequenc- ing issues are avoided. if cs or sclk are applied before v dd , then there is no risk of latch-up as there would be on the analog input if a signal greater than 0.3 v was applied prior to v dd . modes of operation the mode of operation of the AD7476A/ad7477a/ad7478a is selected by controlling the (logic) state of the cs signal during a conversion. there are two possible modes of operation, normal and power-down. the point at which cs is pulled high after the conversion has been initiated will determine whether the AD7476A/ad7477a/ad7478a will enter power-down mode or not. similarly, if already in power-down, then cs can control whether the device will return to normal operation or remain in power-down. these modes of operation are designed to provide flexible power management options. these options can be cho- sen to optimize the power dissipation/throughput rate ratio for differing application requirements. normal mode this mode is intended for the fastest throughput rate perfor- mance, as the user does not have to worry about any power-up times with the AD7476A/ad7477a/ad7478a remaining fully powered all the time. figure 9 shows the general diagram of the operation of the AD7476A/ad7477a/ad7478a in this mode. the conversion is initiated on the falling edge of cs as described in the serial interface section. to ensure the part remains fully powered up at all times, cs must remain low until at least 10 sclk falling edges have elapsed after the falling edge of cs . if cs is brought high any time after the 10th sclk falling edge, but before the end of the t convert , the part will remain powered up, but the conversion will be terminated and sdata will go back into three-state. for the AD7476A, 16 serial clock cycles are required to com- plete the conversion and access the complete conversion results. for the ad7477a and ad7478a, a minimum of 14 and 12 serial clock cycles are required to complete the conversion and access the complete conversion results, respectively. cs may idle high until the next conversion or may idle low until cs returns high sometime prior to the next conversion (effec- tively idling cs low). once a data transfer is complete (sdata has returned to three-state), another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing cs low again. power-down mode this mode is intended for use in applications where slower throughput rates are required; either the adc is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and the adc is then pow- ered down for a relatively long duration between these bursts of several conversions. when the AD7476A/ad7477a/ad7478a is in power-down, all analog circuitry is powered down. to enter power-down, the conversion process must be inter- rupted by bringing cs high anywhere after the second falling edge of sclk and before the 10th falling edge of sclk as shown in figure 10. once cs has been brought high in this window of sclks, then the part will enter power-down, the conversion that was initiated by the falling edge of cs will be terminated, and sdata will go back into three-state. if cs is brought high before the second sclk falling edge, then the part will remain in normal mode and will not power down. this will avoid accidental power-down due to glitches on the cs line. in order to exit this mode of operation and power the AD7476A/ ad7477a/ad7478a up again, a dummy conversion is per- formed. on the falling edge of cs , the device will begin to power up and will continue to power up as long as cs is held low until after the falling edge of the 10th sclk. the device will be fully powered up once 16 sclks have elapsed and valid data will result from the next conversion as shown in figure 11. if cs is brought high before the 10th falling edge of sclk, then the AD7476A/ad7477a/ad7478a will go back into power-down. this avoids accidental power-up due to glitches on the cs line or an inadvertent burst of eight sclk cycles while cs is low. so although the device may begin to power up on the falling edge of cs , it will power down again on the rising edge of cs as long as it occurs before the 10th sclk falling edge. power-up time the power-up time of the AD7476A/ad7477a/ad7478a is 1 s, which means that with any frequency of sclk up to 20 mhz, one dummy cycle will always be sufficient to allow the device to power up. once the dummy cycle is complete, the adc will be fully powered up and the input signal will be ac- quired properly. the quiet time, t quiet , must still be allowed from the point where the bus goes back into three-state after the dummy conversion to the next falling edge of cs . when run- ning at a 1 msps throughput rate, the AD7476A/ad7477a/ ad7478a will power up and acquire a signal within 0.5 lsb in one dummy cycle, i.e., 1 s. when powering up from the power-down mode with a dummy cycle, as in figure 11, the track-and-hold that was in hold mode while the part was powered down returns to track mode after the first sclk edge the part receives after the falling edge of cs . this is shown as point a in figure 11. although at any
rev. 0 AD7476A/ad7477a/ad7478a e15e sclk frequency one dummy cycle is sufficient to power the device up and acquire v in , it does not necessarily mean that a full dummy cycle of 16 sclks must always elapse to power up the device and acquire v in fully; 1 s will be sufficient to power the device up and acquire the input signal. if, for example, a 5 mhz sclk frequency was applied to the adc, the cycle time would be 3.2 s. in one dummy cycle, 3.2 s, the part would be powered up and v in acquired fully. however, after 1 s with a 5 mhz sclk, only five sclk cycles would have elapsed. at this stage, the adc would be fully powered up and the sig- nal acquired. in this case, the cs can be brought high after the 10th sclk falling edge and brought low again after a time, t quiet , to initiate the conversion. when power supplies are first applied to the AD7476A/ad7477a/ ad7478a, the adc may either power up in the power-down or normal mode. because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. likewise, if it is intended to keep the part in the power-down mode while not in use, and the user wishes the part to power up in power-down mode, then the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as that shown in figure 10. once supplies are applied to the AD7476A/ad7477a/ad7478a, the power-up time is the same as that when powering up from the power-down mode. it takes approximately 1 s to power up fully if the part powers up in normal mode. it is not necessary to wait 1 s before executing a dummy cycle to ensure the desired mode of operation. instead, the dummy cycle can occur directly after power is supplied to the adc. if the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that an adequate acquisition time has been allowed. as mentioned earlier, when powering up from the power-down mode, the part will return to track upon the first sclk edge applied after the falling edge of cs . however, when the adc powers up initially after supplies are applied, the track-and-hold will already be in track. this means, assuming one has the facility to monitor the adc supply current, if the adc powers up in the desired mode of operation, and thus a dummy cycle is not required to change the mode, then a dummy cycle is not required to place the track-and-hold into track. power versus throughput rate by using the power-down mode on the AD7476A/ad7477a/ ad7478a when not converting, the average power consumption of the adc decreases at lower throughput rates. figure 12 shows how as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption over time drops accordingly. for example, if the AD7476A/ad7477a/ad7478a is operated in a continuous sampling mode with a throughput rate of 100 ksps and a sclk of 20 mhz (v dd = 5 v), and the device is placed in the power-down mode between conversions, then the power con- sumption is calculated as follows. the power dissipation during normal operation is 17.5 mw (v dd = 5 v). if the power-up time is one dummy cycle, i.e., 1 s, and the remaining conversion va l id data sdata sclk cs 110121 416 AD7476A/ad7477a/ad7478a figure 9. normal mode operation three-state sdata sclk cs 110121 416 2 figure 10. entering power-down mode invalid data sdata sclk cs 110121416 a 116 va l id data the part is fully powered up with v in fully acquired the part begins to power up figure 11. exiting power-down mode
rev. 0 ?6 AD7476A/ad7477a/ad7478a time is another cycle, i.e., 1 s, then the AD7476A/ad7477a/ ad7478a can be said to dissipate 17.5 mw for 2 s during each conversion cycle. if the throughput rate is 100 ksps, the cycle time is 10 s, and the average power dissipated during each cycle is (2/10) (17.5 mw) = 3.5 mw. if v dd = 3 v, sclk = 20 mhz, and the device is again in power-down mode between conversions, then the power dissipation during normal operation is 5.1 mw. the AD7476A/ad7477a/ad7478a can now be said to dissipate 5.1 mw for 2 s during each conversion cycle. with a throughput rate of 100 ksps, the average power dissipated during each cycle is (2/10) (5.1 mw) = 1.02 mw. figure 12 shows the power versus the throughput rate when using the power-down mode between conversions with both 5 v and 3 v supplies. the power-down mode is intended for use with throughput rates of approximately 333 ksps and under, since at higher sampling rates there is no power saving made by using the power-down mode. throughput ?ksps 100 0.1 0 power ?mw 10 1 0.01 50 100 150 200 250 300 350 v dd = 5v, sclk = 20mhz v dd = 3v, sclk = 20mhz figure 12. power vs. throughput serial interface figures 13, 14, and 15 show the detailed timing diagram for serial interfacing to the AD7476A, ad7477a, and ad7478a, respectively. the serial clock provides the conversion clock and also controls the transfer of information from the AD7476A/ ad7477a/ad7478a during conversion. the cs signal initiates the data transfer and conversion process. the falling edge of cs puts the track-and-hold into hold mode and takes the bus out of three-state, and the analog input is sampled at this point. also, the conversion is initiated at this point. for the AD7476A, the conversion will require 16 sclk cycles to complete. once 13 sclk falling edges have elapsed, the track-and- hold will go back into track on the next sclk rising edge as shown in figure 13 at point b. on the 16th sclk falling edge, the sdata line will go back into three-state. if the rising edge of cs occurs before 16 sclks have elapsed, the conversion will be terminated and the sdata line will go back into three-state; otherwise, sdata returns to three-state on the 16th sclk falling edge as shown in figure 13. sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7476A. for the ad7477a, the conversion will require 14 sclk cycles to complete. once 13 sclk falling edges have elapsed the track- and-hold will go back into track on the next rising edge as shown in figure 14 at point b. if the rising edge of cs occurs before 14 sclks have elapsed, the conversion will be terminated and the sdata line will go back into three-state. if 16 sclks are considered in the cycle, sdata will return to three-state on the 16th sclk falling edge, as shown in figure 14. for the ad7478a, the conversion will require 12 sclk cycles to complete. the track-and-hold will go back into track on the rising edge after the 11th falling edge, as shown in figure 15 at point b. if the rising edge of cs occurs before 12 sclks have cs sclk sdata t 2 t 6 t 3 t 4 t 7 t 5 t 8 t convert t q uiet zero zero zero db11 db10 db2 db1 db0 b three-state three- state z 4 leading zeros 12 345 13 14 15 16 t 1 1/throughput figure 13. AD7476A serial interface timing diagram sclk 1 5 13 15 4 leading zeros three-state t 4 2 34 16 t 5 t 3 t 2 db9 db8 db0 zero t 6 t 7 t 8 14 zero zero zero z t 1 1/ throughput zero 2 trailing zeros sdata t convert t q uiet b three-state cs figure 14. ad7477a serial interface timing diagram
rev. 0 AD7476A/ad7477a/ad7478a ?7 elapsed, the conversion will be terminated and the sdata line will go back into three-state. if 16 sclks are considered in the cycle, sdata will return to three-state on the 16th sclk falling edge, as shown in figure 15. cs going low clocks out the first leading zero to be read in by the microcontroller or dsp. the remaining data is then clocked out by subsequent sclk falling edges beginning with the sec- ond leading zero. thus, the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. for the AD7476A, the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. in applications with a slower sclk, it is possible to read in data on each sclk rising edge. in this case, the first falling edge of sclk will clock out the second leading zero and it can be read in the first rising edge. however, the first leading zero that was clocked out when cs went low will be missed, unless it was not read in the first falling edge. the 15th falling edge of sclk will clock out the last bit and it could be read in the 15th rising sclk edge. if cs goes low just after one sclk falling edge has elapsed, cs will clock out the first leading zero as it did before and it may be read in the sclk rising edge. the next sclk falling edge will clock out the second leading zero and it could be read in the following rising edge. ad7478a in a 12 sclks cycle serial interface for the ad7478a, if cs is brought high in the 12th rising edge after the four leading zeros and the eight bits of the conversion have been provided, the part can achieve a 1.2 msps throughput rate. for the ad7478a, the track-and-hold goes back into track in the 11th rising edge. in this case, a f sclk = 20 mhz and a throughput of 1.2 msps gives a cycle time of t 2 +10.5 (1/f sclk ) + t acq = 833 ns. with t 2 = 10 ns min, this leaves t acq to be 298 ns. this 298 ns satisfies the requirement of 225 ns for t acq . from figure 16, t acq is comprised of 0.5 (1/f sclk ) + t 8 + t quiet , where t 8 = 36 ns max. this allows a value of 237 ns for t quiet satisfying the minimum requirement of 50 ns. microprocessor interfacing the serial interface on the AD7476A/ad7477a/ad7478a allows the part to be directly connected to a range of different microprocessors. this section explains how to interface the AD7476A/ad7477a/ad7478a with some of the more common microcontroller and dsp serial interface protocols. AD7476A/ad7477a/ad7478a to tms320c541 interface the serial interface on the tms320c541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices, such as the AD7476A/ad7477a/ad7478a. the cs input allows easy inter- facing between the tms320c541 and the AD7476A/ad7477a/ ad7478a without any glue logic required. the serial port of the tms320c541 is set up to operate in burst mode (fsm = 1 in the serial port control register, spc) with internal serial clock clkx (mcm = 1 in the spc register) and internal frame signal (txm = 1 in the spc register), so both pins are configured as outputs. for the AD7476A, the word length should be set to 16 bits (fo = 0 in the spc register). this dsp only allows frames with a word length of 16 bits or eight bits. therefore, in the case of the ad7477a and ad7478a where 14 bits and 12 bits were required, the fo bit would be set up to 16 bits. this means to obtain the conversion result, 16 sclks are needed. in both situations, the remaining sclks will clock out trailing zeros. for the ad7477a, two trailing zeros will be clocked out in the last two clock cycles; for the ad7478a, four trailing zeros will be clocked out. cs sclk 1 13 15 sdata 4 leading zeros three-state t 4 2 34 16 t 5 t 3 t 2 three-state db7 t 6 t 7 t 8 14 zero zero zero z t 1 1/ throughput zero zero zero zero 11 12 4 trailing zeros t convert t q uiet b figure 15. ad7478a serial interface timing diagram sclk t 1 1 5 11 sdata three-state db7 db6 db0 zero zero zero z 4 leading zeros 2 34 t 2 t 8 12 1/ throughput t acq 10.5(1/fsclk) t convert t q uiet b three-state cs figure 16. ad7478a in a 12 sclk cycle serial interface
rev. 0 e18e AD7476A/ad7477a/ad7478a to summarize, the values in the spc register are: fo = 0 fsm = 1 mcm = 1 txm = 1 the format bit, fo, may be set to
rev. 0 AD7476A/ad7477a/ad7478a e19e to summarize, mod = 0 syn = 1 wl2, wl1, and wl0 depend on the word length fsl1 = 1 and fsl0 = 0 fsp = 1, negative frame sync scd2 = 1 sckd = 1 shfd = 0 it should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the dsp563xx will provide equidistant sampling. AD7476A/ ad7477a ad7478a * sdata sclk cs dsp563xx * sck srd sc2 * a dditional pins omitted for clarity figure 19. interfacing to the dsp563xx application hints grounding and layout the printed circuit board that houses the AD7476A/ad7477a/ ad7478a should be designed such that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should be joined at only one place. if the AD7476A/ad7477a/ ad7478a is in a system where multiple devices require an agnd to dgnd connection, the connection should still be made at one point only, a star ground point which should be established as close as possible to the AD7476A/ad7477a/ad7478a. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the AD7476A/ad7477a/ad7478a to avoid noise coupling. the power supply lines to the AD7476A/ad7477a/ ad7478a should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also very important. the supply should be decoupled with, for instance, a 680 nf 0805 to gnd. when using the sc70 package in applications where the size of the compo- nents is of concern, a 220 nf 0603 capacitor, for example, could be used instead. however, in that case the decoupling may not be as effective and may result in an approximate sinad degradation of 0.3 db. to achieve the best performance from these decoupling components, the user should endeavour to keep the distance between the decoupling capacitor and the v dd and gnd pins to a minimum with short track lengths connectiong the respective pins. figure 20 and 21 show he recommended positions of the decou- pling capacitor for the msop and sc70 package, respectively. as it can be seen in figure 20, for the msop package the decoup- ling capacitor has been placed as close as possible to the ic with short track lengths to v dd and gnd pins. the decoupling capacitor could also be placed on the underside of the pcb directly under- neath the ic, between the v dd and gnd pins attached by vias. this method would not be recommended on pcbs above a stan- dard 1.6 mm thickness. the best performance will be seen with the decoupling capacitor on the top of the pcb next to the ic. figure 20. recommended supply decoupling scheme for the AD7476A/ad7477a/ad7478a msop package similarly, for the sc70 package, the decoupling capacitor should be located as close as possible to the v dd and the gnd pins. because of its pinout, i.e., v dd being next to gnd, the decoupling capacitor can be placed extremely close to the ic. the decoupling capacitor could be placed on the underside of the pcb directly under the v dd and gnd pins, but as before, the best performance will be gotten with the decoupling capaci- tor on the same side as the ic. figure 21. recommended supply decoupling scheme for the AD7476A/ad7477a/ad7478a sc70 package evaluating the AD7476A/ad7477a performance the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the pc via the eval-board controller. the eval-board controller can be used in conjunction with the AD7476A/ad7477acb evaluation board, as well as many other analog devices evaluation boards ending in the cb designator, to demonstrate/evaluate the ac and dc performance of the AD7476A/ad7477a. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the AD7476A/ad7477a. see the evaluation board application note for more information.
rev. 0 ?0 AD7476A/ad7477a/ad7478a outline dimensions 6-lead plastic surface-mount package [sc70] (ks-6) dimensions shown in millimeters 0.22 0.08 0.46 0.36 0.26 8 4 0 0.30 0.15 0.10 max 1.00 0.90 0.70 seating plane 1.10 max 3 5 4 2 6 1 2.00 bsc pin 1 2.10 bsc 0.65 bsc 1.25 bsc 1.30 bsc coplanarity compliant to jedec standards mo-203ab 8-lead msop package [msop] (rm-8) dimensions shown in millimeters 0.23 0.08 0.80 0.40 8 0 85 4 1 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc compliant to jedec standards mo-187aa c02930??/02(0) printed in u.s.a.

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